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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDPCSR, External Debug Program Counter Sample Register</h1><p>The EDPCSR characteristics are:</p><h2>Purpose</h2>
        <p>Holds a sampled instruction address value.</p>
      <h2>Configuration</h2><p>EDPCSR is in the Core power domain.
    </p><p>This register is present only when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented. Otherwise, direct accesses to EDPCSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>EDPCSR[63:32] and EDPCSR[31:0] are accessed at 32-bit memory mapped addresses that are not contiguous.</p>

      
        <p>If <span class="xref">FEAT_VHE</span> is implemented, the format of this register differs depending on the value of <a href="ext-edscr.html">EDSCR</a>.SC2.</p>

      
        <p>Implemented only if the <span class="arm-defined-word">OPTIONAL</span> PC Sample-based Profiling Extension is implemented in the external debug registers space.</p>

      
        <div class="note"><span class="note-header">Note</span><p><span class="xref">FEAT_PCSRv8p2</span> implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.</p></div>
      <h2>Attributes</h2>
        <p>EDPCSR is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When FEAT_VHE is not implemented or EDSCR.SC2 == 0:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">PC Sample high word, EDPCSRhi</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">PC Sample low word</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>PC Sample high word, EDPCSRhi. If <a href="ext-edvidsr.html">EDVIDSR</a>.HV == 0 then this field is RAZ, otherwise bits [63:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from <a href="ext-edvidsr.html">EDVIDSR</a>.{NS,E2,E3}.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-31_0">Bits [31:0]</h4><div class="field"><p>PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value.</p>
<p>EDPCSRlo reads as <span class="hexnumber">0xFFFFFFFF</span> when any of the following are true:</p>
<ul>
<li>The PE is in Debug state.
</li><li>PC Sample-based profiling is prohibited.
</li></ul>
<p>If a branch instruction has retired since the PE left reset state, then the first read of EDPCSR[31:0] is permitted but not required to return <span class="hexnumber">0xFFFFFFFF</span>.</p>
<p>EDPCSRlo reads as an <span class="arm-defined-word">UNKNOWN</span> value when any of the following are true:</p>
<ul>
<li>The PE is in reset state.
</li><li>No branch instruction has retired since the PE left reset state, Debug state, or a state where PC Sample-based Profiling is prohibited.
</li><li>No branch instruction has retired since the last read of EDPCSR[31:0].
</li></ul>
<p>For the cases where a read of EDPCSR[31:0] returns <span class="hexnumber">0xFFFFFFFF</span> or an <span class="arm-defined-word">UNKNOWN</span> value, the read has the side-effect of setting EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a> to <span class="arm-defined-word">UNKNOWN</span> values.</p>
<p>Otherwise, a read of EDPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a>. The translation regime that EDPCSR samples can be determined from <a href="ext-edvidsr.html">EDVIDSR</a>.{NS,E2,E3}.</p>
<p>For a read of EDPCSR[31:0] from the memory-mapped interface, if EDLSR.SLK == 1, meaning the <span class="arm-defined-word">OPTIONAL</span> Software Lock is locked, then the side-effect of the access does not occur and EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a> are unchanged.</p><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h3>When FEAT_VHE is implemented and EDSCR.SC2 == 1:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_1-63_63">NS</a></td><td class="lr" colspan="2"><a href="#fieldset_1-62_61">EL</a></td><td class="lr" colspan="5"><a href="#fieldset_1-60_56">RES0</a></td><td class="lr" colspan="24"><a href="#fieldset_1-55_32">PC Sample high word, EDPCSRhi</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-31_0">PC Sample low word</a></td></tr></tbody></table><h4 id="fieldset_1-63_63">NS, bit [63]</h4><div class="field"><p>Non-secure state sample. Indicates the Security state that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.</p>
<p>If EL3 is not implemented, this bit indicates the Effective value of <span class="xref">SCR</span>.NS.</p><table class="valuetable"><tr><th>NS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Sample is from Secure state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Sample is from Non-secure state.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-62_61">EL, bits [62:61]</h4><div class="field">
      <p>Exception level status sample. Indicates the Exception level that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.</p>
    <table class="valuetable"><tr><th>EL</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Sample is from EL0.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Sample is from EL1.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Sample is from EL2.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Sample is from EL3.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-60_56">Bits [60:56]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-55_32">Bits [55:32]</h4><div class="field">
      <p>PC Sample high word, EDPCSRhi. Bits [55:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-31_0">Bits [31:0]</h4><div class="field"><p>PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value.</p>
<p>EDPCSRlo reads as <span class="hexnumber">0xFFFFFFFF</span> when any of the following are true:</p>
<ul>
<li>The PE is in Debug state.
</li><li>PC Sample-based profiling is prohibited.
</li></ul>
<p>If a branch instruction has retired since the PE left reset state, then the first read of EDPCSR[31:0] is permitted but not required to return <span class="hexnumber">0xFFFFFFFF</span>.</p>
<p>EDPCSRlo reads as an <span class="arm-defined-word">UNKNOWN</span> value when any of the following are true:</p>
<ul>
<li>The PE is in reset state.
</li><li>No branch instruction has retired since the PE left reset state, Debug state, or a state where PC Sample-based Profiling is prohibited.
</li><li>No branch instruction has retired since the last read of EDPCSR[31:0].
</li></ul>
<p>For the cases where a read of EDPCSR[31:0] returns <span class="hexnumber">0xFFFFFFFF</span> or an <span class="arm-defined-word">UNKNOWN</span> value, the read has the side-effect of setting EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a> to <span class="arm-defined-word">UNKNOWN</span> values.</p>
<p>Otherwise, a read of EDPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a>. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.</p>
<p>For a read of EDPCSR[31:0] from the memory-mapped interface, if EDLSR.SLK == 1, meaning the <span class="arm-defined-word">OPTIONAL</span> Software Lock is locked, then the side-effect of the access does not occur and EDPCSRhi, <a href="ext-edcidsr.html">EDCIDSR</a>, and <a href="ext-edvidsr.html">EDVIDSR</a> are unchanged.</p><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing EDPCSR</h2>
        <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> extensions to external debug might make the value of this register <span class="arm-defined-word">UNKNOWN</span>, see <span class="xref">'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'</span></p>
      <h4>EDPCSR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th><th>Range</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x0A0</span></td><td>EDPCSR</td><td>31:0</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register generate an error response.
          </li></ul><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th><th>Range</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x0AC</span></td><td>EDPCSR</td><td>63:32</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register generate an error response.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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